The invention relates generally to computer bus interface circuitry. More particularly, the invention relates to an interface circuit, for connecting one of a selected plurality of different computer buses to the Small Computer System Interface (SCSI) bus. The circuit is well suited for single chip implementation. Dual first in, first out (FIFO) buffers are used to provide a circuit which supports both asynchronous and synchronous modes.
The Small Computer System Interface (SCSI) is a parallel input/output bus often used to connect disc drives, CD-ROMs, tape drives and other peripherals to a computer bus. The SCSI bus is a bidirectional, multimaster bus which can accommodate peer to peer communications among multiple CPUs and multiple peripherals. Because of this versatility, the SCSI bus is becoming increasingly important in the microcomputer field.
There are several popular microcomputer architectures in use today, and for the most part, these architectures are not compatible with one another. For example, the IBM PC XT and AT computer, and the so-called compatibles, use a computer bus which is now popularly called the industry standard architecture (ISA). Some of the more recent IBM microcomputers of the PS/2 family use a different bus known as microchannel architecture (MCA). The microchannel architecture is generally not plug compatible with the earlier industry standard architecture. This has caused some problems in the computer peripheral industry, since manufacturers who want to support both product lines must design different circuits for both architectures. This adds considerably to the cost of developing and supporting peripheral products.
For the engineer wishing to design a SCSI interface into a product to be used across the IBM microcomputer family, there has traditionally been no easy solution. The industry standard architecture and microchannel architecture are sufficiently different that it is not heretofore been possible to design one product for use on both. A great deal of engineering time goes into developing hardware products, and this engineering time is reflected in the product cost. What is needed but has heretofore been unavailable, is a simple, easy to use and cost-effective SCSI controller which may be readily configured to work with either the industry standard architecture or the microchannel architecture.
The present invention implements a complete multifunctional SCSI chip for use with either the ISA architecture or the MCA architecture. The principles may also be used to extend the SCSI circuit to additional architectures such as the Extended Industry Standard Architecture (EISA). In its presently preferred embodiment, the only external requirements are for address decoding at the high order memory address bits, a suitable oscillator and an external static RAM. The static RAM is preferably an 8K.times.8 static RAM used to implement the SCSI controller's main FIFO. Using presently available technology, the external main FIFO is more economically manufactured as a separate component, as opposed to integral with the remainder of the SCSI chip. However, with improvements in chip fabrication technology and with appropriate economies of scale, the entire SCSI chip including main FIFO could be fabricated as a single chip.
The SCSI controller of the invention supports asynchronous and synchronous protocols conforming to the SCSI specification known as the SCSI-II specification proposed by the American National Standards Institute (ANSI) and further described in the X3.131-198x; X3 Project 503-D prepared by the Technical Committee X3T9 of the I/O interface accredited Standards Committee, X3-Information Processing Systems.
The circuit includes logic circuitry for handling SCSI bus arbitration,-automatic generation of acknowledge handshakes, interrupt on SCSI control/data signal, interrupt on SCSI select signal, interrupt on arbitration complete signal and interrupt on SCSI reset signal. The circuit provides first in first out (FIFO) buffering of data-with interrupt generation based on FIFO fullness levels.
The circuit includes an address generator and timing controls for the 8K.times.8 external static RAM used to implement the main FIFO which supports high speed synchronous and asynchronous SCSI device operations. The FIFO data path is I/O mapped to the 16 bit data bus of the host computer. This allows high speed data transfers between the computer bus and the main FIFO. SCSI command information, chip status, setup parameters and data paths are I/O mapped.
The presently preferred chip implementation supports a ROM BIOS space of 7936 (decimal), 1F00 (hex) bytes. The onboard chip logic includes an EPROM enable capability as well as data buffering and latching. An internal memory of 256.times.8 bytes of memory mapped static RAM is provided for use by the ROM BIOS software for variable storage, scratch pad registers and the like.
In one aspect the invention comprises a computer system interface for connection between an input/output SCSI bus and a selected one of at least two different types of host computer bus architectures. The computer system interface of the invention is thus useful in interconnecting a host computer to a peripheral device. The apparatus comprises an internal data bus, a first interface means for coupling the SCSI bus to the internal data bus and a second interface means for coupling the host computer bus to the internal data bus. Control logic gating means are provided for causing data communicated between the SCSI bus and the first interface means to communicate with the internal data bus. The control logic gating means further causes data communicated between the-computer bus and the second interface means to communicate with the internal data bus.
Control signal generation logic means are provided for coupling to the host computer bus. The control signal generation logic means have a first portion adapted for generating control signals of a first type, corresponding to a host computer of a first type. The control signal generation logic means further includes a second portion adapted for generating control signals of a second type, corresponding to a host computer of a second type. User-settable means is provided for selectively enabling one and disabling the other of the first and second portions of the control signal generation logic.
Preferably, the user-settable means defines at least a first state and a second state, each corresponding to different host computer bus architecture types. The user-settable means may be selectively placed in one or the other of the two states by predefined hardware configuration. In the presently preferred embodiment an external conductive lead or terminal is provided for this purpose. Placing this terminal at a first logic state configures the SCSI controller chip as an ISA compatible device, while placing the terminal at a second logical state configures the chip as an MCA compatible device.
In another aspect the invention comprises a computer system interface for connection between a predefined host computer bus and an input/output SCSI bus, for interconnecting a computer to a peripheral device. The apparatus comprises an internal data bus with a main FIFO buffer coupled to it. A first interface means is provided for coupling the SCSI bus to the internal data bus and a second interface means is provided for coupling the host computer bus to the internal data bus. Control logic gating means are provided for causing data communicated between the SCSI bus and the first interface means to flow onto the internal data bus and to further flow from the internal data bus into the main FIFO buffer. Monitoring means are provided for monitoring the quantity of data in the main FIFO buffer and for generating information for placement on the host computer bus as an indication of fullness of the main FIFO buffer.
The monitoring means preferably generates count data which indicates the quantity of data stored in the main FIFO buffer and may also include means for generating an interrupt signal for placement on the host computer bus in the event the quantity of data stored in the main FIFO buffer reaches a predefined level. In this way, software operating on the host computer can access the count data to determine the correct data block size to send or receive. The interrupt signal can serve as an-automatic sentinel to alert the host computer when certain predefined fullness (or emptiness) main FIFO conditions exist.
In the presently preferred embodiment, the first interface comprises an input/output FIFO buffer which may include its own means for monitoring fullness. Depending on the user-selected mode of operation, data communication between host computer bus and SCSI bus may invoke both the main FIFO buffer and the input/output FIFO buffer, the main FIFO buffer only, or neither buffer.
The SCSI controller of the invention is thus very flexible and well adapted for use in a wide variety of SCSI applications. The user-settable computer architecture selection mechanism greatly simplifies SCSI interface circuit design, since the engineer may now design both ISA and MCA peripherals using the same multifunction SCSI chip. Hardware design is facilitated because the engineer is able to apply familiarity gained in developing an ISA SCSI interface to an MCA SCSI interface, and vice-versa. Software design is also facilitated since the multifunction SCSI chip provides a relatively transparent hardware/software interface. The software engineers' task is thus greatly facilitated, since the operating system software can be written with minimal concern about which computer architecture is in place.
For a more complete understanding of the invention and its many objects and advantages, reference may be had to the following detailed specification and to the accompanying drawings.